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? freescale semiconductor, inc., 2005. all rights reserved. freescale semiconductor data sheet mc3phac rev. 2, 7/2005 mc3phac monolithic intelligent motor controller overview the mc3phac is a high-performance monolithic intelli gent motor controller designed specifically to meet the requirements for low-cost, variable-speed, 3-phase ac motor control systems. the device is adaptable and configurable, based on its environment. it contains all of the active functions required to implement the control portion of an open loop, 3-phase ac motor drive. one of the unique aspects of this device is that although it is adaptable and configurable based on its environment, it does not require any software development. this makes the mc3phac a perfect fit for customer applications requiring ac motor control but with limited or no software resources available. the device features are: ? volts-per-hertz speed control digital signal processing (dsp) filtering to enhance speed stability 32-bit calculations for high-precision operation internet enabled no user software development required for operation 6-output pulse-width modulator (pwm) 3-phase waveform generation 4-channel analog-to-digital converter (adc) user configurable for standalone or hosted operation dynamic bus ripple cancellation selectable pwm polarity and frequency selectable 50/60 hz base frequency phase-lock loop (pll) based system oscillator serial communications interface (sci) low-power supply voltage detection circuit included in the mc3phac are protective features consisting of dc bus voltage monitoring and a system fault input that will immediat ely disable the pwm module upon detection of a system fault.
mc3phac monolithic intelligen t motor controller, rev. 2 2 freescale semiconductor overview some target applications for the mc3phac include: low horsepower hvac motors home appliances commercial laundry and dishwashers process control pumps and fans figure 1. mc3phac-based motor control system as shown in table 1 , the mc3phac is offered in these packages: plastic 28-pin dual in-line package (dip) plastic 28-pin small outline integrated circuit (soic) plastic 32-pin quad flat pack (qfp) table 1. ordering information device operating temperature range package mc3phacvp ?40 c to +105 c plastic 28-pin dip MC3PHACVDW ?40 c to +105 c plastic 28-pin soic mc3phacvfa ?40 c to +105 c plastic 32-pin qfp 3-phase ac motor ac in bus voltage feedback resistive brake control pwm?s start/stop forward/reverse speed acceleration pwm frequency mc3phac fault serial interface passive initialization network (optional) to gate drives
overview mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 3 see figure 2 and figure 3 for the pin connections. figure 2. pin connections for pdip and soic figure 3. pin connections for qfp v ref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 reset v dda v ssa osc2 osc1 pllcap pwmpol_basefreq pwm_u_top pwm_u_bot pwm_v_top pwm_v_bot pwm_w_top pwm_w_bot faultin pwmfreq_rxd retry_txd rbrake dt_faultout vboost_mode v dd v ss fwd start mux_in speed accel dc_bus pwm_v_bot pwm_w_top pwm_w_bot faultin v ss pwmfreq_rxd retry_txd rbrake 9 10 11 12 13 14 15 16 pwm_v_top start pwm_u_bot pwm_u_top pwmpol_basefreq pllcap osc1 osc2 v ssa speed mux_in fwd v ss v dd vboost_mode dt_faultout 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 1 v ref v dda reset v ss v ss v ss dc_bus accel
mc3phac monolithic intelligen t motor controller, rev. 2 4 freescale semiconductor electrical characteristics electrical characteristics maximum ratings this device contains circuitry to protect the inputs a gainst damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoi d application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). functional operating range control timing characteristic (1) 1. voltages referenced to v ss symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in ?0.3 to v dd +0.3 v input high voltage v hi v dd + 0.3 v maximum current per pin excluding v dd and v ss i 25ma storage temperature t stg ?55 to +150 c maximum current out of v ss imv ss 100 ma maximum current into v dd imv dd 100 ma characteristic symbol value unit operating temperature range (see ta bl e 1 ) t a ?40 c to +105 c c operating voltage range v dd 5.0 10% v characteristic symbol value unit oscillator frequency (1) 1. follow the crystal/resonator manufactur er?s recommendations, as the crystal/resonator parameters determine the external component values required for maximum stab ility and reliable starting. the load capac itance values used in the oscillator circuit design should include all stray capacitances. f osc 4.00 1% mhz
electrical characteristics mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 5 dc electrical characteristics characteristic (1) 1. v dd = 5.0 vdc 10% symbol min max unit output high voltage (i load = ?2.0 ma) all i/o pins except rbrake v oh v dd ?0.8 ? v output high voltage rbrake (i rbrake = ?15.0 ma) v ohrb v dd ?1.0 ? v output low voltage (i load = 1.6 ma) all i/o pins except faultout and retry/txd v ol ? 0.4 v output low voltage (i load = 15 ma) faultout and retry/txd v ol1 ? 1.0 v input high voltage all ports v hi 0.7 x v dd v dd v input low voltage all ports v il v ss 0.3 x v dd v v dd supply current i dd ? 60 ma i/o ports high-impedance leakage current i il ? 5 a input current i in ? 1 a capacitance ports (as input or output) c out c in ? ? 12 8 pf v dd low-voltage inhibit reset v lv r 1 3.80 4.3 v v dd low-voltage reset/recovery hysteresis v lv h 1 50 150 mv v dd power-on reset re-arm voltage v por 3.85 4.45 v v dd power-on reset rise time ramp rate r por 0.035 ? v/ms serial communications interface baud rate sci bd 9504 9696 bits/sec voltage boost (2) 2. limited in standalone mode to 0 to 35% v boost 0 100 % dead time range (3) 3. limited in standalone mode to 0.5 to 6.0 s dt range 0 31.875 s retry time (4) 4. limited in standalone mode to 0 to ~53 seconds rt time 0 4.55 hours acceleration rate ac rate 0.5 128 hz/sec speed control speed 1 128 hz pwm frequency pwm freq 5.291 21.164 khz high side power transistor drive pump-up time t pump 99 101 ms
mc3phac monolithic intelligen t motor controller, rev. 2 6 freescale semiconductor pin descriptions pin descriptions table 2 is a pin-by-pin functional description of the mc3phac. the pin numbers in the table refer to the 28-pin packages (see figure 2 ). table 2. mc3phac pin descriptions (sheet 1 of 2) pin number pin name pin function 1v ref reference voltage input for the on-chip adc. for best signal-to-noise performance, this pin should be tied to v dda (analog). 2 reset a logic 0 on this pin forces the mc3p hac to its initial startup state. all pwm outputs are placed in a high-impedance mode. reset is a bidirectional pin, allowing a reset of the entire system. it is driven low when an internal reset source is asserted (for example, loss of clock or low v dd ). 3v dda provides power for the analog portions of the mc3phac, which include the internal clock generation circuit (pll) and the adc 4v ssa returns power for the analog portions of the mc3phac, which include the internal clock generation circuit (pll) and the adc 5osc2 oscillator output us ed as part of a crystal or ceramic resonator clock circuit. (1) 6osc1 oscillator input used as part of a crystal or ceramic resonator clock circuit. can also accept a signal from an external canned oscillator. (1) 7pllcap a capacitor from this pin to ground affects the stability and reaction time of the pll clock circuit. smaller values result in faster tracking of the reference frequency. larger values result in bett er stability. a value of 0.1 f is typical. 8 pwmpol_basefreq input which is sampled at specific moments during initialization to determine the pwm polarity and the base frequency (50 or 60 hz) 9 pwm_u_top pwm output signal for the top transistor driving motor phase u 10 pwm_u_bot pwm output signal for the bottom transistor driving motor phase u 11 pwm_v_top pwm output signal for the top transistor driving motor phase v 12 pwm_v_bot pwm output signal for the bottom transistor driving motor phase v 13 pwm_w_top pwm output signal for the top transistor driving motor phase w 14 pwm_w_bot pwm output signal for the bottom transistor driving motor phase w 15 faultin a logic high on this input will imme diately disable the pwm outputs. a retry timeout interval will be initiated once this pin returns to a logic low state. 16 pwmfreq_rxd in standalone mode, this pin is an output that drives low to indicate the parameter mux input pin is reading an analog voltage to specify the desired pwm frequency. in pc master software mode, this pin is an input which receives uart serial data.
pin descriptions mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 7 17 retry_txd in standalone mode, this pin is an output that drives low to indicate the parameter mux input pin is reading an analog voltage to specify the time to wait after a fault before re-enabling the pwm outputs. in pc master software mode, this pin is an output that transmits uart serial data. 18 rbrake output which is driven to a logic high whenever the voltage on the dc bus input pin exceeds a preset level, indicating a high bus voltage. this signal is intended to connect a resist or across the dc bus capacitor to prevent excess capacitor voltage. 19 dt_faultout in standalone mode, this pin is an output which drives low to indicate the parameter mux input pin is reading an analog voltage to specify the dead-time between the on states of the top and bottom pwm signals for a given motor phase. in pc master software mode, this pin is an output which goes low whenever a fault condition occurs. 20 vboost_mode at startup, this input is sampled to determine whether to enter standalone mode (logic high) or pc master software mode (logic low). in standalone mode, this pin is also used as an output that drives low to indicate the parameter mux input pin is reading an analog voltage to specify the amount of voltage boost to apply to the motor. 21 v dd +5-volt digital power supply to the mc3phac 22 v ss digital power supply ground return for the mc3phac 23 fwd input which is sampled to determine whether the motor should rotate in the forward or reverse direction 24 start input which is sampled to determine whether the motor should be running. 25 mux_in in standalone mode, during initialization this pin is an output that is used to determine pwm polarity and base frequency. otherwise, it is an analog input used to read several voltage levels that specify mc3phac operating parameters. 26 speed in standalone mode, during initialization this pin is an output that is used to determine pwm polarity and base frequency. otherwise, it is an analog input used to read a voltage level corresponding to the desired steady-state speed of the motor. 27 accel in standalone mode, during initialization this pin is an output that is used to determine pwm polarity and base frequency. otherwise, it is an analog input used to read a voltage level corresponding to the desired acceleration of the motor. 28 dc_bus in standalone mode, during initialization this pin is an output that is used to determine pwm polarity and base frequency. otherwise, it is an analog input used to read a voltage level proportional to the dc bus voltage. 1. correct timing of the mc3phac is based on a 4.00 mh z crystal or cerami c resonator. follow the crystal/resonator manufacturer?s recommendations, as the cr ystal/resonator parameters determine th e external component values required for maximum stability and reliable starting. the load capacitance values used in the oscillator circuit design should include all stray capacitances. table 2. mc3phac pin descriptions (sheet 2 of 2) pin number pin name pin function
mc3phac monolithic intelligen t motor controller, rev. 2 8 freescale semiconductor introduction introduction the mc3phac is a high-performance in telligent controller designed specif ically to meet the requirements for low-cost, variable-speed, 3-phase ac motor control systems. the device is adaptable and configurable, based on its environm ent. constructed with high-speed cmos (complementary metal- oxide semiconductor) technology, t he mc3phac offers a high degree of performance and ruggedness in the hostile environments often found in motor control systems. the device consists of: 6-output pulse-width modulator (pwm) 4-channel analog-to-digital converter (adc) phase-lock loop (pll) based system oscillator low-power supply voltage detection circuit serial communications interface (sci) the serial communications interface is used in a mode, called pc master software mode, whereby control of the mc3phac is from a host or master personal computer executing pc master software or a microcontroller emulating pc master software commands. in either case, control via the internet is feasible. included in the mc3phac are protective features cons isting of dc bus monitoring and a system fault input that will immediately di sable the pwm module upon detection of a system fault. included motor control features include: open loop volts/hertz speed control forward or reverse rotation start/stop motion system fault input low-speed voltage boost internal power-on reset (por) features 3-phase waveform generation ? the mc3phac generates six pwm signals which have been modulated with variable voltage and variable frequency in formation in order to control a 3-phase ac motor. a third harmonic signal has been superimposed on top of the fundamental motor frequency to achieve full bus voltage utilization. this results in a 15 percent increase in maximum output amplitude compared to pure sine wave modulation. the waveform is updated at a 5.3 khz rate (except when the pwm frequency is 15.9 khz), resulting in near continuous waveform quality. at 15.9 khz, the waveform is updated at 4.0 khz. dsp filtering ? a 24-bit iir digital filter is used on the speed input signal in st andalone mode, resulting in enhanced speed stability in noisy environments. the sampling period of the filter is 3 ms (except when the pwm frequency is 15.9 khz) and it mi mics the response of a single pole analog filter having a pole at 0.4 hz. at a pwm frequency of 15.9 khz, the sampling period is 4 ms and the pole is located at 0.3 hz.
features mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 9 high precision calculations ? up to 32-bit variable resolution is employed for precision control and smooth performance. for example, the motor speed can be controlled with a resolution of 4 mhz. smooth voltage transitions ? when the commanded speed of the motor passes through 1 hz, the voltage is gently applied or removed depending on the di rection of the speed change. this eliminates any pops or surges that may occur, especially under conditions of high-voltage boost at low frequencies. high-side bootstrapping ? many motor drive topologies (especially high-voltage drives) use optocouplers to supply the pwm signal to the high-side transistors. often, the high-side transistor drive circuitry contains a charge pump circuit to create a floating power supply for each high-side transistor that is dependent on low-side pwms to develop power. when the motor has been off for a period of time, the charge on the high-side power suppl y capacitor is depleted and must be replenished before proper pwm operation can resume. to accommodate such topologies, the mc3phac will always provide 100 ms of 50 percent pwm drive to only the low-side transistors each time the motor is turned on. since the top transistors remain off during this time, it has the effect of applying zero volts to the motor, and no motion occurs. after this period, motor waveform modulation begins, with pwm drive also being applied to the high-side transistors. fast velocity updating ? during periods when the motor speed is changing, the rate at which the velocity is updated is critical to smooth operation. if these updates occur too infrequently, a ratcheting effect will be exhibited on the motor, which inhibi ts smooth torque performance. however, velocity profiling is a very calculation intensive operation to perform, which runs contrary to the previous requirement. in the mc3phac, a velocity pipelining technique is employed which allows linear interpolation of the velocity values, resulting in a new velocity value every 189 s (252 s for 15.9 khz pwms). the net result is ultra smooth velocity transi tions, where each velocity step is not perceivable by the motor. dynamic bus ripple cancellation ? the dc bus voltage is sensed by the mc3phac, and any deviations from a predetermined norm (3.5 v on the dc bus input pin) result in corrections to the pwm values to counteract the effect of the bus voltage changes on the motor current. the frequency of this calculation is sufficiently high to permit compensati on for line frequency ripple, as well as slower bus voltage changes resulting from regener ation or brown out conditions. see figure 4 . selectable base frequency ? alternating current (ac) motors are designed to accept rated voltage at either 50 or 60 hz, depending on wh at region of the world they were designed to be used. the mc3phac can accommodate both types of motors by allowing the voltage profile to reach maximum value at either 50 or 60 hz. this parameter can be specified at init ialization in standalone mode, or it can be changed at any time in pc master software mode. selectable pwm polarity ? the polarity of the pwm outputs may be specified such that a logic high on a pwm output can either be the asserted or negat ed state of the signal. in standalone mode, this parameter is specified at initialization and applies to all six pwm outputs. in pc master software mode, the polarity of the top pwm signals can be specifie d separately from the polarity of the bottom pwm signals. this specification can be done at any time, but once it is done, the polarities are locked and cannot be changed until a reset occurs. also, any commands from pc master software that would have the effect of enabling pwms are prevented by the mc 3phac until the polarity has been specified.
mc3phac monolithic intelligen t motor controller, rev. 2 10 freescale semiconductor features figure 4. dynamic bus ripple cancellation in standalone mode, the base frequency and pwm polar ity are specified at the same time during initialization by connecting either pin 25, 26, 27, or 28 exclusively to the pwmpol_basefreq input. during initialization, pins 25, 26, 27, and 28 are cycled one at a time to determine which one has been connected to the pwmpol_basefreq input. table 3 shows the selected pwm polarity and base frequenc y as a function of which pin connection is made. refer to the standalone mode schematic, figure 8 . only one of these jumpers (jp1?jp4) can be connected at any one time. note it is not necessary to break this co nnection once the initialization phase has been completed. the mc3phac will function properly while this connection is in place. table 3. pwm polarity and base frequency specification in standalone mode pin connected to pwmpol_basefreq pin pwm polarity base frequency mux_in (jp1) logic low = on 50 hz speed (jp2) logic high = on 50 hz accel (jp3) logic low = on 60 hz dc_bus (jp4) logic high = on 60 hz ac mains pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 mc3phac corrected pwms motor phase current waveforms uncompensated compensated removes 60 hz hum and decreases i 2 r losses
features mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 11 selectable pwm frequency ? the mc3phac accommodates four discrete pwm frequencies and can be changed dynamically while the motor is running. this resistor can be a potentiometer or a fixed resistor in the range shown in table 4 . in standalone mode, the pwm frequency is specified by applying a voltage to the mux_in pin while the pwmfreq_rxd pin is being driven low. table 4 shows the required voltage levels on the mux_in pin and the associated pwm frequency for each voltage range. note the pwm frequencies are based on a 4.00 mhz frequency applied to the oscillator input. selectable pwm dead time ? besides being able to specify the pwm frequency, the blanking time interval between the on states of the complementary pwm pairs can also be specified. refer to the graph in figure 9 for the resistance value versus dead time. figure 9 assumes a 6.8 k ? 5% pullup resistor. in standalone mode, this is done by supplying a voltage to the mux_in pin while the dt_faultout pin is being driven low. in this way, dead time can be specified with a scaling factor of 2.075 s per volt, with a minimum value of 0.5 s. in pc master software mode, this value can be selected to be anywhere between 0 and 32 s. in both standalone and pc master software modes, the dead time value can be written only once. further updates of this parameter are locked out until a reset condition occurs. speed control ? the synchronous motor frequency can be specified in real time to be any value from 1 hz to 128 hz by the voltage app lied to the speed pin. the scaling fa ctor is 25.6 hz per volt. this parameter can also be controlled directly from pc master software in real time. the speed pin is processed by a 24-bit digital filter to enhance the speed stability in noisy environments. this filter is only activated in standalone mode. acceleration control ? motor acceleration can be specified in real time to be in the range from 0.5 hz/second, ranging to 128 hz/second, by the voltage applied to the accel pin. the scaling factor is 25.6 hz/second per volt. this parameter can also be controlle d directly from pc master software in real time. voltage profile generation ? the mc3phac controls the motor voltage in proportion to the specified frequency, as indicated in figure 5 . an ac motor is designed to draw a specified amou nt of magnetizing current when supplied with rated voltage at the base frequency. as the frequency decr eases, assuming no stator losses, the voltage must decrease in exact proportion to maintain the requir ed magnetizing current. in reality, as the frequency decreases, the voltage drop in the series stator resi stance increases in proportion to the voltage across the magnetizing inductance. this has the effect of further reducing the voltage across the magnetizing inductor, and consequently, the magnetizing current. a schematic representation of this effect is table 4. mux_in resistance ranges and corresponding pwm frequencies voltage input pwm frequency 0 to 1 v 5.291 khz 1.5 to 2.25 v 10.582 khz 2.75 to 3.5 v 15.873 khz 4 to 5 v 21.164 khz
mc3phac monolithic intelligen t motor controller, rev. 2 12 freescale semiconductor features illustrated in figure 6 . to compensate for this voltage loss, the voltage profile is boosted over the normal voltage curve in figure 5 , so that the magnetizing current remains constant over the speed range. figure 5. voltage profiling, including voltage boost figure 6. ac motor single phase model showing parasitic stator impedances the mc3phac allows the voltage boost to be specified as a percentage of full voltage at 0 hz, as shown in figure 5 . in standalone mode, voltage boost is specifie d during the initialization phase by supplying a voltage to the mux_in pin while the vboost_mode pin is being driven low. refer to the graph in figure 11 for the resistance value versus voltage boost. figure 11 assumes a 6.8 k ? pullup resistor. in this way, voltage boost can be specified from 0 to 40 percent, with a scaling factor of 8 percent per volt. in pc master software mode, the voltage boost can be specified from 0 to 100 percent and can be changed at anytime. by using the voltage boost value, and the specified base frequency, the mc3phac has all the information required to generate a voltage profile automatically based on the generated waveform frequency. an additional feature exists in pc master software mode whereby this voltage value can be overridden and controlled in real time. specifying a voltage lower th an the normal volts-per-hertz profile permits a softer torque response in certain ergonomic situations. it also allows for load power factor control and higher operating efficiencies with high inertia loads or other loads where instantaneous changes in torque demand are not permitted. details of this feature are discussed in the pc master software operation with the mc3phac . pll clock generation ? the osc1 pin signal is used as a reference clock for an internal pll clocking circuit, which is used to drive the internal clocks of the mc3phac. this prov ides excellent protection against noise spikes that may occur on the osc1 pin. in a clocking circuit that does not incorporate a pll, a noise spike on the clock input can create a clock ed ge, which violates the setup times of the clocking c o m p e n s a t io n f o r s t a t o r l o s s e s voltage frequency base frequency voltage boost 100% parasitics r 1 x 2 r 2 magnetizing current (try to keep constant) torque current x m r2 (1 ?s) s x 1
features mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 13 logic, and can cause the device to malfunction. the same noise spike applied to the input of a pll clock circuit is perceived by the pll as a change in its reference frequency, and the pll output frequency begins to change in an attempt to lock on to the new frequency. however, before any appreciable change can occur, the spike is gone, and the pll settl es back into the true reference frequency. fault protection ? the mc3phac supports an elaborate range of fault protection and prevention features. if a fault does occur, the mc3phac immediately disables the pwms and waits until the fault condition is cleared before starting a timer to re-enable the pwms. refer to the graph in figure 10 for the resistance value versus retry time. figure 10 assumes a 6.8 k ? pullup resistor. in standalone mode, this timeout interval is specified during the initiali zation phase by supplying a voltage to the mux_in pin while the retry_txd pin is being driven low. in this way, the retry time can be specified from 1 to 60 seconds, with a scaling factor of 12 seconds per volt. in pc master software mode, the retry time can be specified from 0.25 second to over 4.5 hours and can be changed at any time. the fault protection and prevention features are: external fault monitoring ? the faultin pin accepts a digital signal that indicates a fault has been detected via external monitoring circuitry. a high level on this input results in the pwms being immediately disabled. typical faul t conditions might be a dc bus over voltage, bus over current, or over temperature. once this input returns to a logic low level, the fault retry timer begins running, and pwms are re-enabled after the programmed timeout value is reached. lost clock protection ? if the signal on the osc1 pin is lost altogether, the mc3phac will immediately disable the pwm outputs to protect th e motor and power electronics. this is a special fault condition in that it will also cause the mc3phac to be reset. lost clock detection is an important safety consideration, as many sa fety regulatory agencies are now requiring a dead crystal test be performed as part of the certification process. low v dd protection ? whenever v dd falls below v lvr1 , an on-board power supply monitor will reset the mc3phac. this allows the mc3phac to operate properly with 5 volt power supplies of either 5 or 10 percent tolerance. bus voltage integrity monitoring ? the dc_bus pin is monitored at a 5.3 khz frequency (4.0 khz when the pwm frequency is set to 15.9 khz), and any voltage reading outside of an acceptable window constitutes a fault condition. in standalone mode, the window thresholds are fixed at 4.47 volts (128 percent of nominal), and 1.75 volts (50 percent of nominal), where nominal is defined to be 3.5 volts. in pc master software mode, both top and bottom window thresholds can be set independently to any value between 0 volts (0 percent of nominal), and greater than 5 volts (143 percent of nominal), and can be changed at any time. once the dc_bus signal level returns to a value within the acceptable window, the f ault retry timer begins running, and pwms are re- enabled after the programmed timeout value is reached. during power-up, it is possible that v dd could reach operating voltage before the dc bus capacitor charges up to its nominal value. when the dc bus integrity is checked, an under voltage would be detected and treated as a fault, with its associated timeout period. to prevent this, the mc3phac monitors the dc bus voltage during power-up in standalone mode, and waits until it is higher than the under voltage threshold before continuing. du ring this time, all mc3phac functions are suspended. once this threshold is reached, the mc 3phac will continue normally, with any further under voltage conditions treated as a fault. if dc bus voltage monitoring is not desired, a volt age of 3.5 volts 5 percent should be supplied to the dc_bus pin through an impedance of between 4.7 k ? and 15 k ? .
mc3phac monolithic intelligen t motor controller, rev. 2 14 freescale semiconductor features regeneration control ? regeneration is a process by which stored mechanical energy in the motor and load is transferred back into the drive el ectronics, usually as a result of an aggressive deceleration operation. in special cases where this process occurs frequently (for example, elevator motor control systems), it is economical to incorporate special features in the motor drive to allow this energy to be supplied back to the ac mains. however, for most low cost ac drives, this energy is stored in the dc bus capacitor by incr easing its voltage. if this process is left unchecked, the dc bus voltage can rise to dangerous levels, which can destroy the bus capacitor or the transistors in the power inverter. the mc3phac incorporates two techniques to deal with regeneration before it becomes a problem: ? resistive braking ? the dc_bus pin is monitored at a 5.3 khz frequency (4.0 khz when the pwm frequency is set to 15.9 khz), and when the voltage reaches a certain threshold, the rbrake pin is driven high. this signal can be used to control a resistive brake placed across the dc bus capacitor, such that mechanical energy from the motor will be dissipated as heat in the resistor versus being stored as voltage on the capacitor. in standalone mode, the dc_bus threshold required to assert the rbrake signal is fixed at 3.85 volts (110 percent of nominal) where nominal is defined to be 3.5 volts. in pc master software mode, this threshold can be set to any value between 0 volts (0 percent of nominal) and greater than 5 volts (143 percent of nominal) and can be changed at any time. ? automatic deceleration control ? when decelerating the motor, the mc3phac attempts to use the specified acceleration value for deceleration as well. if the voltage on the dc_bus pin reaches a certain threshold, the mc3phac begins to moderate the deceleration as a function of this voltage, as shown in figure 7 . the voltage range on the dc_bus pin from when the deceleration begins to decrease, to when it reaches 0, is 0.62 volts. in standalone mode, the dc_bus voltage where deceleration begins to decr ease is fixed at 3.85 volts (110 percent of nominal) where nominal is defined to be 3.5 volts. in pc master software mode, this threshold can be set to any value between 0 volts (0 percent of nominal) and greater than 5 volts (143 percent of nominal) and can be changed at any time. figure 7. deceleration as a function of bus voltage bus voltage acceleration input deceleration begin moderating decel (level is programmable in pc master software mode)
digital power su pply bypassing mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 15 digital power supply bypassing v dd and v ss are the digital power supply and ground pins for the mc3phac. fast signal transitions connected internally on thes e pins place high, short-duration current demands on the power supply. to prevent noise problems, take sp ecial care to provide power supply bypassing at the v dd and v ss pins. place the bypass capacitors as close as possible to the mc3phac. use a high- frequency-response ceramic capacitor, such as a 0.1 f, paralleled with a bulk capacitor in the range of 1 f to 10 f for bypassing the digital power supply. analog power supply bypassing v dda and v ssa are the power supply pins for the analog portion of the clock generator and analog-to- digital converter (adc). on the schem atics in this document, analog ground is labeled with an a and other grounds are digital grounds. analog po wer is labeled as +5 a. it is good practice to isolate the analog and digital +5 volt power supplies by using a small inductor or a low value resistor less than 5 ohms in series with the digital power supply, to create the +5 a supply. adc v ref is the power supply pin used for setting the adc?s voltage reference. decoupling of these pins should be per the digital power supply bypassing, de scribed previously. adc v ref (pin 1) and v dda (pin 3) shall be connected together and connected to the same potential as v dd . grounding considerations printed circuit board layout is an important design consideration. in particular, ground planes and how grounds are tied together influence no ise immunity. to maximize noise im munity, it is important to get a good ground plane under the mc3phac. it is also impor tant to separate analog and digital grounds. that is why, shown on the schematics, there are two ground designations, analog ground is marked with an a and other grounds are digital grounds. gnd is the digital ground plane and power supply return. gnda is the analog circuit ground. they are both the same reference voltage, but are routed separately, and tie together at only one point. power-up/power-down when power is applied or removed, it is important that the inverter?s top and bottom output transistors in the same phase are not turned on simultaneously. since logic states are not always defined during power- up, it is important to ensure that all power transisto rs remain off when the controller?s supply voltage is below its normal operating level. the mc3phac?s pwm module outputs make this easy by switching to a high impedance configuration whenever the 5-vo lt supply is below its specified minimum. the user should use pullup or pulldown resistors on the output of the mc3phac?s pwm outputs to ensure during power-up and power-down, that the inverter?s drive inputs are at a known, turned off, state.
mc3phac monolithic intelligen t motor controller, rev. 2 16 freescale semiconductor operation operation the mc3phac motor controller will operate in two modes. the first is standalone operation, whereby the mc3phac can be used without any intervention from an external personal computer. in standalone mode, the mc3phac is initialized by passive dev ices connected to the mc3phac and input to the system at power-up/reset time. in standalone mode, some parameters continue to be input to the system as it operates. speed, pwm frequency, bus voltage, and acceleration parameters are input to the system on a real-time basis. the second mode of operation is called pc master software mode.that operational mode requires the use of a personal computer and pc master software executing on the personal computer, communicating with the mc3phac, or a microcontroller emulat ing pc master software commands. all command and setup information is input to the mc3phac via the pc host. standalone operation if the vboost_mode pin is high when the mc3phac is powered up, or after a reset, the mc3phac enters standalone mode. in this mode of operation, the functionality of many of the mc3phac pins change so that the device can control a motor without requiring setup information from an external master. when operated in standalone mode, the mc3phac will dr ive certain pins corresponding to parameters which must be specified, while simultaneously monitoring the response on other pins. in many cases, the parameter to be specified is represented as an analog voltage presented to the mux_in pin, while certain other pins are driven low. in so doing, the mc3phac can accommodate an external analog mux which will switch various signal s on the mux_in pin when the signal select line goes low. all signals must be in a range between 0 v and v ref . as an economical alternative, an external passive network can be connected to each of the param eter select output pins and the mux_in pin, as shown in figure 8 . the thevenin equivalent impedance of this passive network as seen by th e mux_in pin is very important and should be in the range of 5 k ? to 10 k ? . if the resistance is too high, leakage current from the input/output (i/o) pins will cause an offset voltage that will affect the accuracy of the reading. if the resistance is too low, the parameter select pins will not be able to sink the required current for an accurate reading. using a pullup resistor value of 6.8 k ? (as indicated in figure 8 ), the resulting value for each parameter as a function of the corresponding pulldown resistor value is shown in figure 9 , figure 10 , figure 11 , and table 4 . the start input pin is debounced internally and a switch can be directly accommodated on this pin. the input is level sensitive, but a logic 1 level must exist on the pin before a logic 0 level will be processed as a start signal. this will prevent an accidental motor startup in the event of the mc3phac being powered up, where the switch was left in the start position. the fwd input pin is debounced internally and can direct ly accommodate a switch connection. the input is also level sensitive. figure 8 shows the jumper arrangement connected to the pwmpol_basefreq input pin. for proper operation, one and only one jumper con nection can be made at any given time. table 3 shows the polarity and base frequency selections as a f unction of the jumper connection.
operation mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 17 figure 8. standalone mc3phac configuration notes: 1. see figure 11 . 2. see figure 9 . 3. see figure 10 . 4. see table 4 . 5. if no external fault circuit is provided, connect to v ss . 6. connect only one jumper. 7. use bypass capacitors placed close to the mc3phac. 8. consult crystal/resonator manufacturer for component values. jp1 jp2 jp3 jp4 22 pf 22 pf 4.0 mhz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 from divided dc bus +5 v 6.8 k ? note 6 50 hz ? pwm polarity 50 hz + pwm polarity 60 hz ? pwm polarity 60 hz + pwm polarity +5 v 10 k ? reset 0.1 f note 7 +5 a 6 ? pwms to power stage mc3phac +5 a 5 k ? a acceleration pot 4.7 k ? a +5 a 5 k ? a speed pot +5 v 10 k ? start /stop for/rev 10 k ? + 5 + 5 note 7 note 1 note 2 note 3 note 4 from system fault detection circuit to resistive brake driver v ref reset v dda v ssa osc2 osc1 pllcap pwmpol_basefreq pwm_u_top pwm_u_bot pwm_v_top pwm_v_bot pwm_w_top pwm_w_bot dc_bus accel speed mux_in start fwd v ss v dd vboost_mode dt_faultout rbrake retry/txd pwmfreq/rxd faultin note 5 4.7 k ? 0.1 f rpwmfreq rretry rdeadtime rboost note 8 10 m ?
mc3phac monolithic intelligen t motor controller, rev. 2 18 freescale semiconductor operation figure 9. dead time as a function of the rdeadtime resistor figure 10. fault retry time as a function of the rretry resistor figure 11. voltage boost as a function of the rboost resistor 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 012345678910 dead time ( s) resistance (k ? ) 60 55 50 45 40 35 30 25 20 15 10 5 0 0 5 10 15 20 25 30 35 40 45 50 retry time (seconds) resistance (k ? ) 40 35 30 25 20 15 5 0 0 5 10 15 20 25 30 35 40 45 50 vboost (%) resistance (k ? ) 10
operation mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 19 standalone application example figure 12 shows an application example of the mc3p hac, configured in standalone mode. resistor values and jumpers have been selected to provide the following performance: 1. base frequency of 60 hz and positive pwm polarity (from table 3 ) 2. pwm frequency resistor 3.9 k ? , which implies 10.582 khz from table 4 ). (5v/(3.9k + 6.8k))*3.9k = 1.82 volts 3. dead-time resistor = 5.1 k ? , which implies 4.5 s (from figure 9 ) 4. fault retry time resistor = 8.2 k ? , which implies 32.8 seconds (from figure 10 ). 5. voltage boost resistor = 12 k ? , which implies 25.5 percent (from figure 11 ). 6. the wiper of the acceleration potentiometer is set at 2.5 v = 64 hz/second acceleration rate (from the acceleration control description on page 11 .) the potentiometer, in this case, could have been a resistor divider. if a resistor divider is used in place of the acceleration potentiometer, keep the total resistance of the two resistors less than 10 k ? . always use 4.7k ? in series with the center of the acceleration voltage divider resistors, connected to the accel (pin 27) as shown in the application example, figure 12 . 7. crystal/resonator capacitor values are typica l values from the manufacturer. refer to the manufacturers data for actual values. pc master software operation introduction to pc master host software the mc3phac is compatible with freescale ?s pc master host software serial interface protocol. communication occurs over an on-chip uart, on the mc3phac at 9600 baud to an external master device, which may be a microcontroller that also has an integrated uart or a personal computer via a com port. with pc master software, an external cont roller can monitor and c ontrol all aspects of the mc3phac operation. when the mc3phac is placed in pc master software mode, all control of the system is provided through the integrated uart, resident on the mc3phac. inputs such as start, fwd , speed, accel, mux_in, and pwmpol_basefreq have no controllin g influence over operation of the system. even though the speed, start, and fwd inputs are disabled while the system is in pc master software mode, through pc master software, it is possible to monitor the state of those inputs. the most popular master implementation is a pc , where a graphical user interface (gui) has been layered on top of the pc master software command protocol, complete with a graphical data display, and an activex interface. figure 13 shows the mc3phac configured in pc master software mode. it is beyond the scope of this document to describe the pc master software protocol or its implementation on a personal computer. for further information on these topics, refer to other freescale documents relating to the pc master software protocol and availability of pc master host software.
mc3phac monolithic intelligen t motor controller, rev. 2 20 freescale semiconductor operation figure 12. mc3phac application example in standalone mode notes: 1. see figure 11 . 2. see figure 9 . 3. see figure 10 . 4. see table 4 . 5. if no external fault circuit is provided, connect to v ss . 6. use bypass capacitors placed close to the mc3phac. 7. consult crystal/resonator manufacturer for component values. 22 pf 22 pf 4.0 mhz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 from divided dc bus +5 v 6.8 k 50 hz ? pwm polarity 50 hz + pwm polarity 60 hz ? pwm polarity 60 hz + pwm polarity +5 v 10 k reset 0.1 f note 6 +5 a 6 ? pwms to power stage mc3phac +5 a 5 k a acceleration pot 4.7 k a +5 a 5 k a speed pot +5 v 10 k start /stop for/rev 10 k + 5 + 5 note 6 note 1 note 2 note 3 note 4 from system fault detection circuit to resistive brake driver v ref reset v dda v ssa osc2 osc1 pllcap pwmpol_basefreq pwm_u_top pwm_u_bot pwm_v_top pwm_v_bot pwm_w_top pwm_w_bot dc_bus accel speed mux_in start fwd v ss v dd vboost_mode dt_faultout rbrake retry/txd pwmfreq/rxd faultin note 5 4.7 k 0.1 f rpwmfreq rretry rdeadtime rboost note 7 10 m nc nc nc 12 k 5.1 k 8.2 k 3.9 k
operation mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 21 figure 13. mc3phac configuration for using a pc as a master pc master software operation with the mc3phac when power is first appl ied to the mc3phac, or if a logic low level is applied to the reset pin, the mc3phac enters pc master software mode if the vboost_mode pin is low during the initialization phase. the mc3phac recognizes a subset of the pc master software command set, which is listed in table 5 . with the readvarx commands, the addresses are checke d for validity, and the command is executed only if the address is within proper limits. in g eneral, a read command with an address value below $0060 or above $ee03 will not execute properly, but instead will return an invalid operation response. an table 5. recognized pc host software commands command description getinfobrief mc3phac responds with brief summary of hardware setup and link configuration information readvar8 mc3phac reads an 8-bit variable at a specified address and responds with its value readvar16 mc3phac reads a 16-bit variable at a specified address and responds with its value readvar32 mc3phac reads a 32-bit variable at a specified address and responds with its value writevar8 mc3phac writes an 8-bit variable at a specified address writevar16 mc3phac writes a 16-bit variable at a specified address notes: 1. if no external fault circuit is provided, connect to v ss . 2. use bypass capacitors placed close to the mc3phac. 3. consult crystal/resonator ma nufacturer for component values. 22 pf 22 pf 4.0 mhz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 from divided dc bus +5 v 10 k reset 0.1 f note 2 +5 a 6 ? pwms to power stage mc3phac a + 5 note 2 from system fault detection circuit to resistive brake driver v ref reset v dda v ssa osc2 osc1 pllcap pwmpol_basefreq pwm_u_top pwm_u_bot pwm_v_top pwm_v_bot pwm_w_top pwm_w_bot dc_bus accel speed mux_in start fwd v ss v dd vboost_mode dt_faultout rbrake retry/txd pwmfreq/rxd faultin 10 k 0.1 f note 3 10 m +5 v 10 k +5 v fault led 560 data to pc data from pc isolated or non-isolated rs232 interface connection to host note 1
mc3phac monolithic intelligen t motor controller, rev. 2 22 freescale semiconductor operation exception to this rule is that pc master softwar e allows reading locations $0001, $0036 and $fe01, which are portb data register, dead time register and sim reset status registers respectively. the addresses for the writevarx commands are checked for validity, and the data field is also limited to a valid range for each variable. see table 6 for a list of valid data va lues and valid write addresses. user interface variables and their associated pc master software addresses within the mc3phac are listed in table 6 . table 6. user interface variables for use with pc master software name address read/ write size (bytes) description valid data commanded direction $1000 w 1 determines whether the motor should go forward, reverse, or stop forward ? $10 reverse ? $11 stop ? $20 command reset $1000 w 1 forces the mc3phac to perform an immediate reset $30 commanded pwm frequency (1) $1000 w 1 specifies the frequency of the mc3phac pwm frequency 5.3 khz ? $41 10.6 khz ? $42 15.9 khz ? $44 21.1 khz ? $48 measured pwm period $00a8 r 2 the modulus value supplied to the pwm generator used by the mc3phac ? value is multiplied by 250 ns to obtain pwm period $00bd?$05e8 commanded pwm polarity (2), (3), (4) $1000 w 1 specifies the polarity of the mc3phac pwm outputs. this is a write once parameter after reset. example: $50 = bottom and top pwm outputs are positive polarity. b + t + $50 b + t ? $54 b ? t + $58 b ? t ? $5c dead time (2), (3), (4) $0036 r/w 1 specifies the dead time used by the pwm generator. dead time = value * 125 ns. this is a write-once parameter. $00?$ff base frequency (3) $1000 w 1 specifies the motor frequency at which full voltage is applied 60 hz ? $60 50 hz ? $61 acceleration (3) $0060 r/w 2 acceleration in hz/sec (7.9 format) (8) $0000?$7fff commanded motor frequency (3) $0062 r/w 2 commanded frequency in hz. (8.8 format) (9) $0000?$7fff actual frequency $0085 r 2 actual frequency in hz. (8.8 format) (9) $0000?$7fff status (7) $00c8 r 1 status byte $00?$ff voltage boost $006c r/w 1 0 hz voltage. %voltage boost = value/$ff $00?$ff modulation index $0091 r 1 voltage level (motor waveform amplitude percent assuming no bus ripple compensation) modulation index = value/$ff $00?$ff
operation mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 23 maximum voltage $0075 r/w 1 maximum allowable modulation index value %maximum voltage = value/$ff $00?$ff v bus voltage (5), (10) $0079 r 2 dc bus voltage reading $000?$3ff fault timeout $006a r/w 2 specifies the delay time after a fault condition before re-enabling the motor. fault timeout = value * 0.262 sec $0000?$ffff fault timer $006d r 2 real-time display of the fault timer elapsed fault time = value * 0.262 sec $0000?$ffff v bus decel value (10) $00c9 r/w 2 v bus readings above this value result in reduced deceleration. $0000?$03ff v bus rbrake value (10) $0064 r/w 2 v bus readings above this value result in the rbrake pin being asserted. $0000?$03ff v bus brownout value (10) $0066 r/w 2 v bus readings below this value result in an under voltage fault. $0000?$03ff v bus over voltage value (10) $0068 r/w 2 v bus readings above this value result in an over voltage fault. $0000?$03ff speed in adc value (5) $0095 r 2 left justified 10-bit adc reading of the speed input pin. $0000?$ffc0 setup (7) $00ae r 1 bit field indicating which setup parameters have been initialized before motion is permitted $e0?$ff switch in (7) $0001 r 1 bit field indicating the current state of the start/stop and forward/reverse switches $00?$ff reset status (6), (7) $fe01 r 1 indicates cause of the last reset $00?$ff version $ee00 r 4 mc3phac version ascii field 1. the commanded pwm frequency cannot be written until the pw m outputs exit the high-impeda nce state. the default pwm frequency is 15.873 khz. 2. the pwm output pins remain in a high-im pedance state until this par ameter is specified. 3. this parameter must be specified before motor motion can be initiated by the mc3phac. 4. this is a write-once parameter. the fi rst write to this address will execute norm ally. further attempts at writing this parameter will result in an illegal operation response from the mc3phac. 5. the value of this parameter is not valid until the pwm outputs exit the high-impedance state. 6. the data in this field is only valid for one read. further reads will return a value of $00. 7. see register bit descriptions following this table. 8. acceleration is an unsigned value with the upper seven bits range of $00 to $7f = acceleration value of 0 to 127 hertz/second. the lower nine bits constitute the fractional portion of the acceleration parameter. its range is $000 to $1ff which equals 0 to ~1. theref ore, the range of acceleration is 0 to 127.99 hertz/second. 9. commanded motor frequency and actual frequency are signed values with the upper byte range of $00 to $7f = frequency of 0 to 127 hz. the lower byte is t he fractional portion of the frequency. its range is $00 to $ff which equals 0 to ~1. 10. v bus is the voltage value applied to the dc_bus analog input pin. the analog-to-digital converter is a 10-bit converter with a 5 volt full scale input. the value is equal to the voltage applied to the dc_bus input pin/v ref * $03ff. table 6. user interface variables for use with pc master software (continued) name address read/ write size (bytes) description valid data
mc3phac monolithic intelligen t motor controller, rev. 2 24 freescale semiconductor operation each bit variable listed in table 6 is defined in figure 14 , figure 15 , figure 16 , and figure 17 . address: $00c8 76543210 r speed changing forward motion motor energized resistive brake external fault trip over voltage trip under voltage trip w resetu0100u00 = unimplemented or reserved u = unaffected figure 14. status register table 7. status register field descriptions field description 6 speed changing speed changing bit ? this read-only bit indicates if the motor is at a steady speed or if it is accelerating or declerating. 0 motor is at a steady speed. 1 motor is accelerating or decelerating. 5 forward motion forward motion bit ? this read-only bit indicates the dire ction of the motor. it also indicates if the motor is stopped. 0 motor is rotating in the reverse direction. 1 motor is rotating in the forward direction. if this bit is a logic 1 and the actual frequency (location $0085 and $0086) is 0, the motor is stopped. 4 motor energized motor energized bit ? this read-only bit indicates pwm output activity 0 the pwm outputs are inactive or the bottom pwm outputs are in the pre-charge cycle. 1 all pwm outputs are active. 3 resistive brake resistive break bit ? this read-only bit indicates the state of the rbrake output pin 0 the rbrake output pin is inactive and no braking is in progress. 1 the rbrake output pin is acti ve. braking is in progress. 2 external fault trip external fault trip bit ? this read-only bit indicates a fault has occurred resulting from a logic 1 applied to the faultin pin. 0 a logic 0 is applied to the faultin pin and no fault timeout is in progress. 1 a logic 1 was applied to the faultin pin and a fault timeout is still in progress. 1 over voltage trip over-voltage trip bit ? this read-only bit indicates if the voltage at the dc_bus pin exceeds the preset value of v bus over voltage located at address $0068 and $0069. 0 the voltage applied to the dc_bus pin is less than the preset value of v bus over voltage and a fault timeout is not in progress. 1 the voltage applied to the dc_bus pin has exceeded the preset value of v bus over voltage and a fault timeout is still in progress. 0 under voltage trip under-voltage bit ? this read-only bit indicates if th e voltage at the dc_bus pin is less than the present value of v bus brownout located at address $0066 and $0067. 0 the voltage applied to the dc-bus pin is greater than the preset value of v bus under voltage and a fault timeout is not in progress. 1 the voltage applied to the dc_bus pin is less than the present value of v bus under voltage and a fault timeout is still in progress.
operation mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 25 address: $00ae 76543210 r base frequency set speed set acceleration set polarity set dead time set w reset111 0 0 0 0 0 = unimplemented or reserved figure 15. setup register table 8. setup register field descriptions field description 4 base frequency set base frequency set bit ? this read-only bit indicates if the base frequency parameter has been set. 0 base frequency parameter has not been set. 1 base frequency parameter has been set. 3 speed set speed set bit ? this read-only bit indicates if the speed parameter has been set. 0 speed parameter has not been set. 1 speed parameter has been set. 2 accelera- tion set acceleration set bit ? this read-only bit indicates if the acceleration rate parameter has been set. 0 acceleration rate parameter has not been set. 1 acceleration rate parameter has been set. 1 polarity set polarity set bit ? this read-only bit indicates if the pwm polarity parameters has been set. 0 pwm polarity parameters has not been set. 1 pwm polarity parameters has been set. 0 dead time set dead time set bit ? this read-only bit indicates if the dead time parameter has been set. 0 dead time parameter has not been set. 1 dead time parameter has been set.
mc3phac monolithic intelligen t motor controller, rev. 2 26 freescale semiconductor operation address: $0001 76543210 r start / stop fwd / reverse fault out resistor brake w resetuuuuu0uu = unimplemented or reserved u = unaffected figure 16. switch in register table 9. switch in register field descriptions field description 6 start / stop start /stop bit ? this read-only bit indicates the state of the start input pin. 0 the start input pin is at a logic 0. 1 the start input pin is at a logic 1. 5 fwd / reverse fwd /reverse bit ? this read-only bit indicates the state of the fwd input pin. 0the fwd input pin is at a logic 0 1the fwd input pin is at a logic 1 3 fault out fault out bit ? this read-only bit indicates the state of the dt_faultout output pin. 0 the dt_faultout output pin is indicating a fault condition. 1 the dt_faultout output pin is indicating no fault condition. 2 resistor brake resistive brake bit ? this read-only bit indicates the st ate of resistive brake pin (rbrake). 0 the rbrake output pin in inactive and no braking is in progress. 1 the rbrake output pin in active. braking is in progress.
operation mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 27 address: $fe01 76 5 4 3210 r power up reset pin mc3phac functional fault mc3phac functional fault pc master software reset command low v dd voltage w reset10 0 0 0000 = unimplemented or reserved figure 17. reset status register table 10. reset status register field descriptions field description 7 power up power up bit ? this read-only bit indicates the last system reset was caused by the power-up reset detection circuit. 0 power-up reset was not the source of the reset or a read of the reset status register after the first read. 1 the last reset was caused by an initial power-up of the mc3phac. 6 reset pin reset pin bit ? this read-only bit indicates the last system reset was caused from the reset input pin. 0 the reset pin was not the source of the reset or a read of the reset status register after the first read. 1 last reset was caused by an exte rnal reset applied to the reset input pin. 5?4 mc3phac functional fault bits mc3phac functional fault bits ? this read-only bit indicates if the last system reset was the result of an in ternal system error. 0 the functional fault was not the source of the reset or a read of the reset status register after the first read. 1 mc3phac internal system error pc master software reset command pc master software reset command bit ? this read-only bit in dicates the last system reset was the result of a pc master software reset command. 0 the pc master software reset command was no t the source of the re set or a read of the reset status register after the first read. 1 the mc3phac was reset by the pc master software command reset as the result of a write of $30 to location $1000 1 low v dd voltage low v dd voltage bit ? this read-only bit indi cates if the last reset was the result of low v dd applied to the mc3phac. 0the low v dd was not the source of the reset or a read of the reset status register after the first read. 1 the last reset was caused by the low power supply detection circuit.
mc3phac monolithic intelligen t motor controller, rev. 2 28 freescale semiconductor operation command state machine when using the pc master software mode of operat ion, the command state machine governs behavior of the device depending upon its current state, system parameters, any new commands received via the communications link, and the prev ailing conditions of the system. the command state diagram is in figure 18 . it illustrates the sequence of commands which are necessary to bring the device from the reset condition to running the motor in a steady state and dep icts the permissible state transitions. the device will remain within a given state unless t he conditions shown for a transition are met. some commands only cause a temporary state change to occur. while they are being executed, the state machine will automatically return to the state which existed prior to the command being received. for example, the motor speed may be c hanged from within any state by using the writevar16 command to write to the "speed in" variable. this will cause the "set speed" state to be momentarily entered, the "speed in" variable will be updated and then the original state will be re-entered. this allows the motor speed, acceleration or base frequency to be modifi ed whether the motor is already accelerating, decelerating, or in a steady state. each state is described here in more detail. reset ? this state is entered when a device power-on re set (por), pin reset, loss of crystal, internally detected error, or reset command occurs fr om within any state. in this state, the device is initialized and the pwm outputs are configured to high impedance. this state is then automatically exited. pwmhighz ? this state is entered from the reset state. this state is also re-entered after one and only one of the pwm dead-time or polarity parameters have been initialized. in this state the pwm outputs are configured to a high-impedance state as the device waits for both the pwm dead time and polarity to be initialized. setdeadtime (write once) ? this state is entered from the pwmhighz state the first time that a write to the pwm dead-time variable occurs. in this state, the pwm dead time is initialized and the state is then automatically exited. this state cannot be re-entered, and hence the dead time cannot be modified, unless the reset state is first re-entered. setpolarity (write once) ? this state is entered from the pwmhighz state the first time that the pwm polarity command is received. in this state, the pwm polarity is initialized and the state is then automatically exited. this state cannot be re-entered, and hence the polarity cannot be modified, unless the reset state is first re-entered. pwmoff ? this state is entered from the pwmhighz state if both the pwm dead time and polarity have been configured. in this state, th e pwm is activated and all the pwm outputs are driven off for the chosen polarity. the device then waits for the pwm base frequency, motor speed, and acceleration to be initialized. pwm0rpm ? this state is entered from the pwmoff state when the pwm base frequency, motor speed, and acceleration have been initialized. this state can also be entered from the fwddecel or revdecel states if a cmdstop command has been received, and the actual motor speed has decelerated to 0 r.p.m. in this state, the pwm pins are driven to the off state for the chosen polarity. the only exit of this state is to the pwmpump state, which occurs when a cmdfwd or cmdrev command is received.
operation mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 29 figure 18. pc host software command state diagram pwmhighz reset fwddecel fwdaccel pwm0rpm setpolarity (write once) setdeadtime (write once) fwdsteady revaccel revdecel revsteady cmdreset reset or por or loss of crystal or internal error initialized cmdpwmtxbx d o n e done w r i t e v a r8 : de a d - t i m e pwm base freq. set & acceleration set & speed in set c m d s t o p & a c t u a l s p e e d = 0 cmdrev | cmdstop cmdfwd | cmdstop actual speed = speed in actual speed = speed in speed in > actual speed speed in > actual speed ( s p e e d i n < a c t u a l s p e e d ) | c m d f w d | c m d s t o p ( s p e e d i n < a c t u a l s p e e d ) | c m d r e v | c m d s t o p setspeed writevar16:speed in from any state done (return to calling state) setspeed writevar16:speed in from any state done (return to calling state) setaccel writevar16:acceleration from any state done (return to calling state) setaccel writevar16:acceleration from any state done (return to calling state) execute pc master cmd other pc master command from any state done (return to calling state) execute pc master cmd other pc master command from any state done (return to calling state) pwm dead-time set & pwm polarity set pwmoff setbasefreq cmdbasefreqxx from any state done (return to calling state) setbasefreq cmdbasefreqxx from any state done (return to calling state) fault fault f a u l t r e m o v e d & f a u l t t i m e o u t d o n e cmdfwd | cmdrev pwmpump c m d s t o p & a c t u a l s p e e d = 0 cmdfwd & actual speed = 0 done & cmdfwd done & cmdrev cmdrev & actual speed = 0 pc master software command from any state
mc3phac monolithic intelligen t motor controller, rev. 2 30 freescale semiconductor operation pwmpump ? this state is entered from the pwm0rpm state when a cmdfwd or cmdrev command is received. in this state the top pwm outputs are driven off while the bottom pwm outputs are driven with a 50 percent duty cycle. th is allows high side transistor gate drive circuits which require charge pumping from the lower trans istors to be charged up prior to applying full pwms to energize the motor. this state is automatically exited after the defined amount of time t pump (see electrical characteristics ). fwdaccel ? this state is entered from the pwmpump state after a cmdfwd command is received and the timeout interval from the pwmpump state is completed. this state can also be entered from the fwdsteady state if the speed in variable is increased above the actual current speed and the revdecel state if the actual motor speed equals 0 r.p.m. when a cmdfwd command has been received. in this state the motor is accelerated forward according to the chosen parameters. fwdsteady ? this state is entered from the fwdaccel state after the actual motor speed has reached the requested speed defined by the speed in variable. in this state, the motor is held at a constant forward speed. fwddecel ? this state is entered from the fwdaccel or fwdsteady states whenever a cmdstop or cmdrev command is received. this state can also be entered from the fwdsteady state if the speed in variable is decreased below the actual current speed. in this state, the motor is decelerated forward according to the chosen parameters. revaccel ? this state is entered from the pwmpump state. after a cmdrev command is received and the timeout interval from the pwmpump state is completed. this state can also be entered from the revsteady state if the speed in variable is increased above the actual current speed and the fwddecel state if the actual moto r speed equals 0 r.p.m. when a cmdrev command has been received. in this state, the motor is accelerated in reverse according to the chosen parameters. revsteady ? this state is entered from the revaccel state after the actual motor speed has reached the requested speed defined by the speed in variable. in this state, the motor is held at a constant reverse speed. revdecel ? this state is entered from the revaccel or revsteady states whenever a cmdstop or cmdfwd command is received. this state can also be entered from the revsteady state if the speed in variable is decreased below the actual current speed. in this state, the motor is decelerated in reverse according to the chosen parameters. setbasefreq ? this state is entered from any state whenever a cmdbasefreqxx command is received. in this state, the motor frequency at which full voltage is applied is configured and the state is then automatically exited and the original state is re-entered. setaccel ? this state is entered from any state w henever a write to the acceleration variable occurs. in this state, the motor acceleration is configured and the state is then automatically exited and the original state is re-entered. setspeed ? this state is entered from any state whenever a write to the speed in variable occurs. in this state, the requested motor speed is confi gured and the state is then automatically exited and the original state is re-entered. fault ? this state is entered from any state whenever a fault condition occurs (see fault protection on page 13 ). in this state, the pwm outputs are driven off (unless the fault state was entered from the pwmhighz state, in which case, the pwm outputs remain in the high z state). when the problem causing the faul t condition is removed, a timer is started which will wait a specified amount of time (which is user program mable) before exiting this state. under normal
optoisolated rs232 interf ace application example mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 31 operating conditions, this timeout will cause the fault state to be automatically exited to the pwm0rpm state, where motion will once again be initiated if a cmdfwd or cmdrev has been received. the exceptions to this rule are the cases when the fault state was entered from the pwmhighz or pwmoff states, in which case, exiting from the fault state will return back to these states. optoisolated rs232 interf ace application example some motor control systems have the control elec tronics operating at the same potential as the high voltage bus. connecting a pc to that system could pr esent safety issues, due to the high voltage potential between the motor control system and the pc. figure 19 is an example of a simple circuit that can be used with the mc3phac to isolate the serial por t of the pc from the motor control system. the circuit in figure 19 is the schematic of a half-duplex optoiso lated rs232 interface. this isolated terminal interface provides a margin of safety be tween the motor control system and a personal computer. the eia rs232 specification states the signal levels can range from 3 to 25 volts. a mark is defined by the eia rs232 specification as a signal that ranges fr om ?3 to ?25 volts. a space is defined as a signal that ranges from +3 to +25 volts. therefore, to meet the rs232 specification, signals to and from a terminal must transition through 0 volts as it changes from a mark to a space. breaking the circuit down into an input and output section simpli fies the explanation of the circuit. figure 19. optoisolated rs232 circuit to send data from a pc to the mc3phac, it is necessa ry to satisfy the serial input of the mc3phac. in the idle condition, the serial input of the mc3phac must be at a logic 1. to accomplish that, the transistor in u1 must be turned off. the idle state of the transmit data line (txd) fr om the pc serial port is a mark (?3 to ?25 volts). therefore, the diode in u1 is off and the transistor in u1 is off, yielding a logic 1 to the mc3phac?s serial input. when the start bit is sent to the mc3phac from the pc?s serial port, the pc?s txd transitions from a mark to a space (+3 to +25 volts), thus forward biasing the diode in u1. forward biasing the diode in d1 turns on the transistor in u1 , providing a logic 0 to the serial input of the mc3phac. simply stated, the input half of the circuit provides input isolation, signal inversion, and level 5 9 4 8 3 7 2 6 1 gnd dtr txd rts rxd d3 1n4148 d2 1n4148 r3 4.7 k d1 1n4148 r1 1 k 1 2 + c1 2.2 f/50 v ~+12 v 4 5 u1 4n35 u2 4n35 +5 v to mc3phac pin 17 4 5 1 2 r4 330 +5 v r2 1 k to mc3phac pin 16 isolation barrier rs232 isolated half-duplex, maximum 9600 baud j1 con/cannon9 female
mc3phac monolithic intelligen t motor controller, rev. 2 32 freescale semiconductor optoisolated rs232 interface application example shifting from the pc to the mc3phac?s serial port. an rs-232 line receiver, such as an mc1489, serves the same purpose without the optoisolation function. to send data from the mc3phac to the pc?s serial port input, it is necessary to satisfy the pc?s receive data (rxd) input requirements. in an idle condition, the rxd input to the pc must be at mark (?3 to ?25 volts). the data terminal ready output (dtr) on the pc outputs a mark when the port is initialized. the request to send (rts) output is set to a space (+3 to +25 volts) when the pc?s serial port is initialized. because the interface is half-duplex, the pc?s txd output is also at a mark, as it is idle. the idle state of the mc3phac?s serial port output is a l ogic 1. the logic 1 out of the mc3phac?s serial port output port forces the diode in u2 to be turned off. with the diode in u2 turned off, the transistor in u2 is also turned off. the junction of d2 and d3 are at a mark (?3 to ?25 volts). with the transistor in u2 turned off, the input is pulled to a mark through current limiti ng resistor r3, satisfying t he pc?s serial input in an idle condition. when a start bit is sent from the mc3phac?s serial port, it transitions to a logic 0. that logic 0 turns on the diode in u2, thus turning on the transis tor in u2. the conducting transistor in u2 passes the voltage output from the pc?s rts output, that is now at a space (+3 to +25 volts), to the pc?s receive data (rxd) input. capacitor c1 is a bypass capacitor used to stiffen th e mark signal. the output half of the circuit provides output isolation, signal inversio n, and level shifting from the mc3phac?s serial output port to the pc?s serial port. an rs-232 line driver , such as a mc1488, serves the same purpose without the optoisolation function.
mechanical data mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 33 mechanical data this subsection provides case outline drawings for: plastic 28-pin dip, figure 20 plastic 28-pin soic, figure 21 plastic 32-pin qfp, figure 22 figure 20. plastic 28-pin dip (case 710) figure 21. plastic 28-pin soic (case 751f)

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mc3phac monolithic intelligen t motor controller, rev. 2 34 freescale semiconductor mechanical data figure 22. plastic 32-pin qfp (case 873a) 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae?ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?ab? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?t?, ?u?, and ?z? to be determined at datum plane ?ab?. 5. dimensions s and v to be determined at seating plane ?ac?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?ab?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc detail ad a1 b1 v1 4x s 4x b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref 9 ?t? ?z? ?u? t?u 0.20 (0.008) z ac t?u 0.20 (0.008) z ab 0.10 (0.004) ac ?ac? ?ab? m 8x ?t?, ?u?, ?z? t?u m 0.20 (0.008) z ac
mechanical data mc3phac monolithic intelligen t motor controller, rev. 2 freescale semiconductor 35
mc3phac rev. 2, 7/2005 how to reach us: usa/europe/locations not listed: freescale semiconductor literature distribution p.o. box 5405, denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: freescale semiconductor japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: freescale semiconductor h.k. ltd. 2 dai king street tai po industrial estate tai po, n.t. hong kong 852-26668334 learn more: for more information about freescale semiconductor products, please visit http://www.freescale.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale semiconductor assume any liability arising out of the application or use of any product or ci rcuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or s pecifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2004.

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